The dual damascene process is often adopted in semiconductor fabrication when feature sizes are scaled down and/or technology nodes exist in the submicron level. In the dual damascene process, copper is often used as conductive material for interconnection. Other conductive materials include tungsten, titanium, titanium nitride, and so forth. With these examples, inter-level dielectric (ILD) may include silicon oxide, fluorinated silica glass, or low dielectric constant (k) materials. Chemical mechanical polishing (CMP) processing is often implemented to etch back and globally planarize the ILD and conductive materials. CMP involves both mechanical grinding and chemical etching in the material removal process. However, because the removal rate of metal and dielectric materials are usually different, polishing (such as CMP) can lead to undesirable dishing and erosion effects. The surface level variation may approach or exceed a depth of focus for a lithography process used in further processing, which thereby degrades exposure and patterning resolution.
It is desired to reduce surface level variation due to processes like CMP, and improve exposure and patterning resolution for processes such as lithography.